(a) Field of the Invention
The present invention relates to a phase locked loop (PLL) having a phase/frequency comparator block and, more particularly, to the structure of a phase/frequency comparator block in a PLL circuit for supplying a binary coded output for the result of the comparison. The present invention also relates to such a phase/frequency comparator block.
(b) Description of the Related Art
A PLL circuit is generally used in a microprocessor to generate a higher frequency clock signal from a lower frequency reference signal, the clock signal being in synchronism with the reference signal. A circuit configuration for a digital PLL circuit is described by Hata and Furukawa in 8th section of "DIGITAL PLL in Use of PLL-IC", (edited by Akiba Co., 1991), for example. A digital PLL circuit generally comprises a phase comparator for supplying a binary coded output for the result of the phase comparison and a voltage controlled oscillator (VCO) receiving the binary coded output through a digital filter. This type of phase comparator can be implemented by a data flip-flop circuit.
An all-digital PLL circuit comprising a phase comparator for supplying a binary coded output is described by J. Dunning et al., in "An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessor", pp, 660-670, IEICE Transaction on Electronics, June 1995.
FIG. 1 shows a conventional digital PLL circuit 10 comprising a phase comparator 11 for supplying a binary coded output to a digital controller 13 for controlling a VCO 15. The digital PLL circuit 10 also has a frequency comparator 12 for supplying a binary coded output to the digital controller 13. The frequency comparator 12 is disposed to provide a pull-in function for the digital PLL circuit 10 in a frequency acquisition mode before the phase comparator 11 functions for phase comparison in a phase acquisition mode. The changeover between the frequency acquisition mode and the phase acquisition mode in the digital PLL circuit 10 is executed by a switching circuit, not shown, after the pull-in is completed.